1. Field of the Invention
The present invention generally relates to the transfer of data in a computer system. More particularly, the present invention relates to transferring data between multiple computer busses. Still more particularly, the present invention relates to a system in which data may be broadcast from a bus master device on one computer bus to multiple target devices on a different bus.
2. Background of the Invention
Computer systems have achieved wide usage in modem society. During operation, a computer system processes and stores data at a speed and at a level of accuracy many times that which can be performed manually. Successive generations of computer systems have permitted increasingly large amounts of data to be processed at faster rates.
Computer systems are sometimes operated as stand-alone devices or connected together by way of network connections, typically together with a network server, to form a computer network. When networked together, communication between the separate computer systems is possible. Files and other data stored or generated at one computer system can be transferred to another computer system.
A conventional computer system typically includes one or more Central Processing Units (CPUs) capable of executing software applications, and a computer main memory. Peripheral devices, both those embedded together with a CPU or constructed to be separate therefrom, also typically form part of a conventional computer system. Computer peripheral devices include, for instance, video graphics adapters, Local Area Network (LAN) interfaces, Small Computer System Interface (SCSI) bus adapters, and mass storage devices, such as disk drive assemblies.
A computer system further typically includes computer buses which permit communication of data between various components of the computer system. For example, a host bus, a memory bus, a local peripheral expansion bus, and one or more additional peripheral buses form portions of a typical computer system. A peripheral bus may comprise, for example, a Small Computer Systems Interface (SCSI) bus, an Extension to Industry Standard Architecture (EISA) bus, an Industry Standard Architecture (ISA) bus, or a Peripheral Component Interface (PCI) bus. The peripheral bus forms a communication path to and from one or more peripheral devices connected thereto. The peripheral bus typically links the peripheral devices to a bus bridge, which in turn couples to the CPU.
The computer operates by having data flow through the system, with modification of the data occurring frequently. Traditionally, the CPU controlled most activities in the computer system. The CPU supervises data flow and is responsible for most of the high-level data modification in the computer. The CPU, therefore, is the “heart” of the system and receives signals from the peripheral devices, reads and writes data to memory, processes data, and generates signals controlling the peripheral devices.
Despite the importance of the processor, the performance of the computer system is determined only in part by the speed and efficiency of the processor. Other factors also affect system performance. One of the most critical factors is the bus that interconnects the various system components. The size and clock speed of the bus dictate the maximum amount of data that can be transmitted between components. Early bus systems, such as the ISA (Industry Standard Architecture) bus, required that all components communicate through the CPU. The ISA bus was a bus standard adopted by computer manufacturers to permit the manufacturers of peripheral devices to design devices that would be compatible with most computer systems.
Since the introduction of the ISA bus, computer technology has continued to evolve at a relatively rapid pace. New peripheral devices have been developed, and processor speeds and the size of memory arrays have increased dramatically. In conjunction with these advances, designers have sought to increase the ability of the various system busses to transfer more data at a faster speed. One way in which the system busses have been made more efficient is to permit data to be exchanged in a computer system without the assistance of the CPU. To implement this design, however, a new bus protocol had to be developed. One of the first such buses that permitted peripheral devices to run master cycles independently of the CPU was the EISA (Extended Industry Standard Architecture) bus. The EISA bus enables various system components residing on the EISA bus to obtain mastership of the bus and to run cycles on the bus.
More recently, the Peripheral Component Interconnect (PCI) bus has become increasingly popular. Like the EISA bus, the PCI bus has bus master capabilities, and thus certain master components residing on the PCI bus may communicate directly with other PCI components by addressing read and write commands to these other components based on protocols defined in the PCI Specification, which has been jointly developed by companies in the computer industry. Because of the bus mastering capabilities and other advantages of the PCI bus, many computer manufacturers now implement the PCI bus as one of the primary expansion busses in the computer system.
As one skilled in the computer art will appreciate, computer peripheral devices originate from numerous manufacturers. Thus, it is commonplace for a computer system to include a CPU from one manufacturer, with a variety of peripheral devices that originate from other manufacturers. Furthermore, the software platform for the computer system may comprise any of several different operating systems. Software drivers typically are required for each computer peripheral device to effectuate its operation. A software driver must be specifically tailored to operate in conjunction with the particular operating system operating on the computer. A multiplicity of software drivers might have to be created for a single computer peripheral to ensure that device is operable with any of the different possible operating systems that may be used as the software platform for the computer system.
The complexity resulting from such a requirement has led, at least in part, to the development of an Intelligent Input/Output (I2O) standard specification. The I2O standard specification sets forth, inter alia, standards for an I/O device driver architecture that is independent of both the specific peripheral device being controlled and the operating system of the computer system to which the device driver is to be installed. In the I2O standard specification, the portion of the driver that is responsible for managing the peripheral device is logically separated from the specific implementation details of the operating system with which it is to be installed. Because of this, the part of the driver that manages the peripheral device is portable across different computer and operating systems. The I2O standard specification also generalizes the nature of communications between the host computer system and peripheral hardware; thus, providing processor and bus technology independence.
Regardless of which bus protocol is deployed in a computer system or whether the computer system is I2O compliant, devices frequently employ bus master/slave functionality to communicate across a computer system bus. In a typical bus transaction, a single bus master sends information, including, but not limited to, address, data and control information to a single target device operating as a slave during that bus transaction. In certain situations, however, it is desirable to broadcast the information to multiple targets. For example, in a fault-tolerant environment it is desirable to perform fast backup of data such as by providing mirrored disk drives. Conventional methods for broadcasting information to multiple targets requires moving the information multiple times using multiple bus transactions.
It would be advantageous therefore, to devise a method and apparatus, which would effectuate low-latency distribution of data to multiple devices. It would further be advantageous if such a method and apparatus provided multicasting on a computer system bus wherein information from a single bus master is broadcast to multiple targets during a single bus transaction.
In addition, it also would be desirable if broadcast cycles could be performed across different busses, without requiring the cycles to be relayed to each target device by the bus bridge. Currently, a master on a first bus must target the bus bridge, which operates as a slave device. Once the bus bridge receives the cycle, the bus bridge operates as a master on the second bus bridge to relay the cycle to a target on the second bus. This process must be repeated for each target on the second bus. This repetitive process of relaying signals can degrade performance on both busses. In computer systems that implement multiple peripheral or system busses, coupled together by bridges, it would be desirable if a master on one bus could transmit multicast cycles to all targeted devices on any bus by having the bridge relay the multicast signal a single time. The ability to broadcast messages to multiple devices on different busses would further reduce system latency that would otherwise result if cycles must be repeated to each target.